IIT Roorkee GlobalFoundries Project Associate 2026: 0.45V SRAM Research, One Walk-in Seat

GlobalFoundries-linked 0.45-V semiconductor research at IIT Roorkee

IIT Roorkee's Department of Electronics and Communication Engineering has announced one Project Associate for the GF University Centre, sponsored by GlobalFoundries, U.S. Inc. and led by Prof. Anand Bulusu. The signed notice is dated 14 October 2026. This is a one-year research-project position, not a regular IIT teaching or permanent technical-cadre appointment. The work is centred on digital/semiconductor intellectual-property development for energy-efficient low-voltage systems on chip (SoCs).

Read before you travel: official interview time is inconsistent

The IIT Roorkee Project Jobs listing says 24 October 2026 at 11:00 AM, whereas the signed three-page original PDF, page 3, specifies the same date but 3:00 PM at the HoD Conference Room, Electronics & Communication Engineering Department. Both sources are on IIT Roorkee's own website. The recruitment PDF does not state which time supersedes the other or publish a corrigendum in the checked sources. Confirm the actual reporting/interview time with the department at +91-1332-285347 or vlsi-office@ece.iitr.ac.in before travelling. Do not infer a reporting cutoff from either listing.

Eligibility: broad notified degrees, specialised actual research

The official qualification line literally lists B.Tech / B.Arch / M.Sc. / M.A. as alternatives. It does not specify an essential engineering branch, minimum marks/CGPA, required experience duration, GATE/NET qualification, numerical upper age limit or discipline restriction in that qualifications line. Consequently, do not silently replace its broad degree wording with an invented compulsory M.Tech, VLSI certification or minimum three-year semiconductor-industry requirement. The institute may assess role fit at interview; a qualifying degree alone is not a guarantee of selection.

The job description is substantially more specialised than the academic entry list: the institute wants work on ultra-low-voltage logic and SRAM/memory-cell IP, standard-cell libraries, timing/power/energy/leakage models, circuit simulation, synthesis, static timing analysis (STA), process-voltage-temperature (PVT) variation and programming capability including Python/MATLAB. These are notified project activities and expected expertise; they must not be misrepresented as separate formal degree or certification eligibility requirements.

What 0.45 V and 32 kHz mean for the actual vacancy

The project targets SoC always-on operation and 0.45-V retention supply, including standard-cell and memory-cell characterisation under PVT/process variations. Its named 32-kHz RTC wake-up circuits are an always-on design target. Candidates familiar with timing closure, power/leakage estimation and variation-aware design can present concrete examples of their own work. Do not invent a tape-out milestone, specific PDK node, foundry technology, EDA vendor, benchmark power-saving percentage, access to proprietary GF tools or guaranteed chip-fabrication opportunity: none is specified in the notice.

The project describes opportunities for PhD/MS by Research, possible industry internship with GlobalFoundries, industry exposure and research publications. The phrasing is explicitly about opportunities, not automatic admission, placement, internship entitlement or confirmed authorship. The PDF separately repeats that the selected candidate may get an opportunity for PhD admission.

Emoluments and tenure without assumed monthly pay

The signed notice states ₹35,000–₹40,000 + HRA and duration: one year. It does not specify a monthly/daily/annual pay period, HRA rate, salary-fixation formula, starting amount for a given qualification, deduction treatment or an extension promise. Hence this record preserves the numeric range with an unspecified/other payment period. Do not publish a presumed monthly take-home figure or a 7th CPC pay level for this project opening.

Application and interview procedure

The original notice accepts supporting documents by email or allows them to be produced at interview. The stated application email is vlsi-office@ece.iitr.ac.in; required materials listed are CV, degree certificates and experience certificates (where applicable). Applicants attending in person are asked to carry original degree and experience certificates for verification. The project notice does not set a separate clock-time deadline for emailed documents. Do not invent an online registration portal, application fee or admissions application.

An in-person walk-in interview is specified for 24 October 2026 at IIT Roorkee's ECE department, subject to the 11 AM versus 3 PM conflict described above. The institute says no TA/DA is payable for attending the interview and indicates SC/ST preference when qualifications and experience are equal; this is not a declared category-wise vacancy roster or an age-relaxation table. The successful applicant is expected to join as soon as possible, but no exact joining date is announced.

Recruitment lifecycle: what exists and what is not announced

Officially stated: project vacancy and dated advert; email/on-arrival document submission; walk-in interview; original-certificate verification; joining as soon as possible if selected. Not announced: separate written examination, exam pattern or syllabus, exam admit card, answer key, numerical qualifying cutoff, published result date, selected-candidate list and interview scoring formula. Therefore those lifecycle arrays are left empty rather than populated with guessed events.

Sources: original signed PDF and IIT Roorkee Project Jobs listing. Check for any later departmental correction before travelling or publishing a definitive clock time.